Fabrication of integrated circuits and other microelectronic devices include processes to fill features formed in or on a substrate. For example, such features may be filled with a conductive material to form a conductive pathway between devices or regions of an integrated circuit or microelectronic device. In some processes, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), or atomic layer deposition (ALD) can be used to deposit material onto the substrate and within the features. These processes can be used to form a layer along the surfaces of the feature and/or to completely fill the feature.
The inventors have observed that using typical deposition processes with ever-shrinking semiconductor devices results in the buildup of overhang in the features and the incapability to provide sufficient step coverage (e.g., coverage on bottom and sidewalls of the feature as compared to the top surface of the substrate), or more specifically, sidewall coverage with no overhang on the feature top. In particular, the undesirable buildup of material near the upper opening of the features, referred to as overhang, can cause the opening of the feature to be closed off prematurely, undesirably forming a pocket, or void, where no material is present.
Accordingly, the inventors have developed improved techniques to etch a substrate via atomic layer deposition cycles.